The runtime system uses these low-level atomic operations to implement all its
multi-threading primitives.  This patch provides ARM implementations of these.

--- ghc-6.10.2.orig/includes/SMP.h	2009-03-31 06:13:15.000000000 +1300
+++ ghc-6.10.2/includes/SMP.h	2009-06-18 15:54:37.000000000 +1200
@@ -104,7 +104,12 @@
 	: "+r" (result), "+m" (*p)
 	: /* no input-only operands */
       );
+#elif arm_HOST_ARCH
+    __asm__ __volatile__ ("swp %0, %1, [%2]"
+                         : "=&r" (result)
+                         : "r" (w), "r" (p) : "memory");
 #elif !defined(WITHSMP)
+#error xchg() unimplemented on this architecture
     result = *p;
     *p = w;
 #else
@@ -148,7 +153,23 @@
 	: "memory"
     );
     return n;
+#elif arm_HOST_ARCH
+    StgWord result,tmp;
+
+    __asm__ __volatile__(
+        "1:     ldrex   %1, [%2]\n"
+        "       mov     %0, #0\n"
+        "       teq     %1, %3\n"
+        "       strexeq %0, %4, [%2]\n"
+        "       teq     %0, #1\n"
+        "       beq     1b\n"
+                : "=&r"(tmp), "=&r"(result)
+                : "r"(p), "r"(o), "r"(n)
+                : "cc","memory");
+
+    return result;
 #elif !defined(WITHSMP)
+#error cas() unimplemented on this architecture
     StgWord result;
     result = *p;
     if (result == o) {
@@ -181,6 +202,8 @@
 #elif sparc_HOST_ARCH
     /* Sparc in TSO mode does not require write/write barriers. */
     __asm__ __volatile__ ("" : : : "memory");
+#elif arm_HOST_ARCH
+    __asm__ __volatile__ ("" : : : "memory");
 #elif !defined(WITHSMP)
     return;
 #else